1. Field of the Invention
The present invention generally relates to ferromagnetic thin film memories and sensors and, more particularly, relates to high density magnetic memory devices and sensors and methods of manufacturing therefor.
2. Description of the Prior Art
Digital memories of various kinds are used extensively in computer and computer system components, digital processing systems and the like. Such memories can be formed, to considerable advantage, based on the storage of digital bits as alternative states of magnetization of magnetic materials in each memory cell, typically thin-film materials. These films may be thin ferromagnetic films having information stored therein based on the direction of the magnetization occurring in those films. The information is typically obtained either by inductive sensing to determine the magnetization state, or by magnetoresistive sensing of each state.
Such ferromagnetic thin-film memories may be conveniently provided on the surface of a monolithic integrated circuit to thereby provide easy electrical interconnection between the memory cells and the memory operating circuitry on the monolithic integrated circuit. When so provided, it is desirable to reduce the size and increase the packing density of the ferromagnetic thin-film memory cells to achieve a significant density of stored digital bits.
Typically, a thin-film magnetic memory includes a number of bit lines intersected by a number of word lines.
At each intersection, a thin film of magnetically coercive material is interposed between the corresponding word line and bit line. The magnetic material at each intersection forms a magnetic memory cell in which a bit of information is stored.
The word lines are often provided on a first metal interconnect layer and the bit lines are provided on another. In each case, the metal interconnect layers must typically be connected to supporting circuitry or other underlayer structures on the monolithic integrated circuit for the memory to function. In addition, portions of the first metal interconnect layer are often connected to portions of the second metal interconnect layer to complete selected circuit elements.
When connecting a first interconnect layer with certain underlayers like poly runners or field areas, a contact structure is typically used. A contact structure includes an opening through a dielectric layer separating the underlayers and the first interconnect layer, which is then filled by the first interconnect layer or more preferably a plug. A plug is typically made from tungsten or similar material having high conductivity, and often enables the contact structure to be reduced in size while maintaining an acceptable contact resistance.
When connecting a second interconnect layer with another interconnect layer, such as the first interconnect layer, a via structure is typically used. A via structure typically includes an opening through the dielectric layer separating the corresponding interconnect layers, which is then filled by one of the interconnect layers, or more preferably a plug. As described above, a plug is typically made from tungsten or similar material having high conductivity, and enables the via structure to be reduced in size while maintaining an acceptable via resistance.
In a typical semiconductor fabrication process, plug processing, and in particular tungsten plug processing, is performed at a relatively high temperature such as greater than 450.degree. C. These high temperatures can often damage or otherwise reduce the effectiveness of the magnetic materials in the bit region of a memory cell. Since the bit region is typically formed before the contacts or vias, the bit region would be subjected to the relatively high temperatures associated with contact and via processing when provided.
Accordingly, conventional magnetic RAM processes forego the use of contact and via plugs. Thus, to achieve an acceptable contact and via resistance, the size of the contact and via structures must typically be increased. Likewise, the size of the metal interconnect layers must be increased to meet the minimum overlap rules associated with most integrated circuit processes. This in-turn reduces the packing density that can be achieved for the memory device.